MFCO=Val_0x0
DMA Channel 0 Dropped Packet Counter Register
MFC | Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programingthe ETH_DMA_CH0_CONTROL[RPF] field. The counter gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. |
MFCO | Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incrementedfurther. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0 (Val_0x0): Miss frame counter overflow not occurred 1 (Val_0x1): Miss frame counter overflow occurred |